Systems software. Firmware. Network infrastructure.
Jialong Wang
I build close to the hardware boundary, where clocks, buses, routers, logs, and validation pipelines have to agree.
About Me
I got hooked the first time a board stayed silent and the only way forward was a scope trace and a stubborn hypothesis.
I gravitate to the lowest layers: clocks, registers, buses, and the thin slice of firmware that makes hardware honest. Most of my work is bring-up, driver debugging, and building repeatable validation pipelines. I like systems that can explain themselves, where every log line and timing edge has a reason.
Status Update / Summer 2026
Working on TRex integration with Cisco 8000 NPU traffic generation as a Software Engineer II Intern.
Writeups
Longer notes on systems, bring-up, validation, and infrastructure work.
- Cisco 8000 NPU TGen: TRex-compatible traffic testing Ongoing
- Sending patches to Git: review discipline, revisions 2026-03
- TahoeOS: smartwatch firmware, bootloader, and BLE control path Ongoing
- MicroKernel-MPU: hardware-first bringup and fault triage Ongoing
- ARM SoC bring-up: early-stage failures and stability fixes 2025-08
- Production computer vision inspection pipeline 2024-08
- FreeRTOS firmware for continuous environmental sensing 2024-04
- BMS validation automation and signal integrity 2022-09
- Compliance data pipeline for 4M+ records 2021-08
Notes
Shorter field notes, checklists, and debug workflows.
- MicroKernel-MPU, seam, and wire: one debug story 2026-03
- Bring-up debug checklist 2025-09
- I2C/SPI/UART timing gotchas 2025-06
- Production CV pipeline notes 2024-06
- FreeRTOS scheduling triage 2025-08
- MPU sandbox permission faults 2025-07
- UART CLI fast debug workflow 2025-06